Showing 200 Results of about 401 Jobs
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Check Out the Median Salary for Verilog
(2009-11-21)
Senior ASIC Design Engineer - Storage
Modicom    (San Jose, CA)
ASIC, Storage, Verilog, VHDL, RTL, SATA Senior ASIC Design Engineer - Storage Requirements: --Define the architecture of new product --Verilog RTL design and coding... with Verilog RTL design --Familiar with Verilog simulation and synthesis tools from Candence   HOTJOB
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(2009-11-20)
High Speed
Modicom    (San Jose, CA)
been through the entire ASIC design cycle (Verilog, Synopsys Design Compiler, Prime Time, BIST/SCAN   HOTJOB
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(2009-11-20)
CPU Verification Engineer
Modicom    (Santa Clara, CA)
Asic, Asic Verification, RTL, Verilog, and Systems Verilog CPU Verification EngineerVerilog and C PLI --Experienced with the formal verification, code coverage, and logic simulators (i.e. NCVerilog, VCS). --Created and debugged tests for Verilog designs --Utilized   HOTJOB
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(2009-11-20)
Digital Systems Engineer
BrainHunter    (Atlanta, GA)
knowledge of Verilog hardware description language.o Demonstrated Technical Project Leadership... with customers, internal users and system engineers.o Translate specified requirements to Verilog... synthesis & simulationo Verilog programming and coding practiceso Timing analysiso Hardware   DICE
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(2009-11-21)
Design Implementation Engineer
InMata Solutions Inc    (San Jose, CA)
Qualifications(Required Skills & Experience) Direct knowledge of Various CAD tools and techniques such DC, DC-topo, Primetime STA, Spyglass, Formality, conformal LEC, and Verilog simulator with Verdi Experience with big SoC level netlist handling. Good script   LEARN4GOOD
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(2009-11-21)
Senior Design Verification Engineer
Etech Resources    (Chandler, AZ)
back-annotated timing . Participate in compliance testing. Proficient in System Verilog and random constraint... Verilog. Proficient in Synopsys VCS. Proficient in Synopsys VMM . Familiar with DPI calls to and from   DICE
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(2009-11-21)
Applications Engineer Job in San Jose 95134, California
Altera Corporati...    (San Jose, CA)
, RLDRAM II, and QDRII. Experience debugging Verilog / VHDL. Experience with hardware, IP bring-up   MONSTER
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(2009-11-21)
Applications Engineer
Altera Corporation    (San Jose, CA)
/>Experience debugging Verilog / VHDL. Experience with hardware, IP bring-up and data   HOTJOB
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(2009-11-21)
Sr. Digital Design Engineer
Synaptics, Inc.    (Santa Clara, CA)
technologies. You should have good knowledge of RTL coding using Verilog, logic synthesis, timing   HOTJOB
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(2009-11-21)
Staff - Sr Staff Software Engineer - Synthesis
Tabula, Inc    (Santa Clara, CA)
/> Requirements: Deep understanding of Verilog and VHDL design and synthesis. Strong   HOTJOB
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